pub fn rom_read8_kernel(address: b8) -> In<b32, 8>Expand description
A read-only SyncBRAM input: read address, never write.
RHDL’s SyncBRAM always has a write port. A ROM is simply a RAM whose
write enable is tied to false. Synthesis sees the constant and removes
the write logic. Input: an 8-bit address. Output: the RAM input bundle
for a 256 × 32-bit memory. Purely combinational; the read result appears
on the RAM’s output one clock later.