Function compression_pipeline_unchecked_verilog 

pub fn compression_pipeline_unchecked_verilog() -> Result<String, RHDLError>

Renders the complete pipeline without invoking RHDL’s external syntax check.

This is only generation evidence. Before FPGA use, an independent HDL parser, equivalence simulation, and synthesis must accept the exact bytes.

Errors

Propagates lowering and rendering errors.