pub fn round_pipeline_kernel<const STAGES: usize>(
clock_reset: ClockReset,
input: CompressionInput,
q: Q<STAGES>,
) -> (CompressionOutput, D<STAGES>)where
W<STAGES>: BitWidth,Expand description
Connects fixed-phase stages and aligns resettable validity with data/tag.
Inputs: clock_reset, the new request input, and q (every register’s
current value). Outputs: the result leaving the last stage and d (every
register’s next value). Timing: a request entering at clock t leaves at
clock t + STAGES, and a new one may enter every clock.