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round_pipeline_verilog

rhdl_dsig_scalable_core::blake3_core

Function round_pipeline_verilog 

Source 
pub fn round_pipeline_verilog<const STAGES: usize>() -> Result<String, RHDLError>
where
    W<STAGES>: BitWidth,
Expand description

Emits a checked BLAKE3 pipeline or small test prefix as Verilog.

ยงErrors

Returns RHDL lowering/rendering errors or an error from its external syntax checker. A successful string is not a synthesis, timing, or hardware result.