pub fn haraka512_verilog() -> Result<String, RHDLError>Expand description
Generates the complete twenty-stage pipeline’s RHDL-authored Verilog.
§Errors
Returns an RHDL lowering/rendering/syntax-check error. Successful rendering alone is not synthesis, timing closure, equivalence, or hardware evidence.
This is how the RHDL source becomes Verilog for Vivado: RHDL “lowers” the kernels to its intermediate form and prints Verilog modules.