pub fn message_reader_kernel(
clock_reset: ClockReset,
input: ReaderInput,
q: MessageReaderQ,
) -> (ReaderOutput, MessageReaderD)Expand description
The reader’s logic.
Runs once per clock and has four parts, in the order of a message’s journey: issue read addresses (AR), store returned beats in the FIFO (R → FIFO), free slice buffers that were taken, and unpack the head beat into the next slice’s buffer (unpack + deal).
- Inputs:
clock_reset, theReaderInput(host settings, memory signals, per-slicetaken), andq, the current FIFO output, control and data registers. - Outputs: the
ReaderOutputandMessageReaderD, the next register values plus this clock’s FIFO read and write ports. - Timing: a message dealt in cycle
tappears asvalidto its slice in cyclet + 1(the outputs come from registers); a slice’stakenin cycletlets a new message be dealt into its buffer in cyclet + 1.