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SIGN_LATENCY_CYCLES

Constant SIGN_LATENCY_CYCLES 

Source
pub const SIGN_LATENCY_CYCLES: f64 = 173.0;
Expand description

Idle signing latency: native simulation (cycle-accurate RHDL, not the card) of the slice signer behind the uBFT service’s request stream (tests/ubft_signer.rs, 2 slices, 8 isolated requests after the first certificate: 171–188 cycles, mean 173.1, every frame the reference signature). A key is cached and its certificate made, so this is the message digest, the 68-cycle schedule slot it waits for, the node reads from the key cache, the 26-beat frame and the relay registers. It replaces an unmeasured 64-cycle estimate (28 BLAKE3 + 26 beats + ~10 registers) that left out the schedule wait and the cache reads. The batch kernel’s HBM reader and writer add their own cycles (not measured).

Unit: clock cycles. The planner uses it for idle latency and, with Little’s law, for the number of signatures in flight.