pub fn table_lane(rounds: u32) -> (f64, f64)Expand description
LUTs and BRAM36 of one Haraka lane with its first rounds table rounds
(0..=6, from round 3).
The two ends are builds: 0 is the routed v3 lane (HARAKA_LANE_LUT),
6 the lane derived from v5’s synthesis (HARAKA_TABLE_LANE_LUT). In
between, the LUT saving is interpolated per table lookup (352 lookups
save 16,445 LUTs, ~46.7 each) and the block RAM is exact: two lookups per
dual-port BRAM18, so a quarter of a BRAM36 per lookup. This is the lever
for a BRAM-bound chip: fewer table rounds per lane cost LUTs but free
block RAM for more lanes.