pub fn slice_chain_kernel<const TABLE_MASK: usize>(
clock_reset: ClockReset,
input: SliceChainInput,
q: SliceChainEngineQ<TABLE_MASK>,
) -> (SliceChainOutput, SliceChainEngineD<TABLE_MASK>)Expand description
Wiring for SliceChainEngine: salt, cascade, and carry earlier nodes.
Timing, for a chain presented at cycle t (L = lane latency):
| Cycle | Event |
|---|---|
t | enters depth 0 with salt index; carry stage 0 loaded |
t + L | depth 0 result enters depth 1 (salt index + 68) and carry stage L |
t + 2L | depth 1 result enters depth 2 (salt index + 136) and carry stage 2L |
t + 3L | depth 2 result and the carried nodes 0..2 leave together |
Output valid is forced low during reset; ready is the AND of the
three lanes’ ready flags (UltraRAM S-boxes loaded).