Function cache_address_kernel 

pub fn cache_address_kernel(slot: b9, chain: b7) -> b16

Dense cache row of (slot, chain): slot × 68 + chain.

68 = 64 + 4, so this is two shifts and two adds. A power-of-two layout (slot << 7 | chain) would waste 60 of every 128 rows and need 1,024 UltraRAMs for 512 keys per slice, more than the U280’s 960.

Inputs: slot (9 bits, 0..512) and chain (7 bits, 0..68). Output: the 16-bit row address. Purely combinational: the result is ready in the same cycle.