pub fn slice_factory_kernel<const TABLE_MASK: usize>(
clock_reset: ClockReset,
input: SliceFactoryInput,
q: SliceFactoryQ<TABLE_MASK>,
) -> (SliceFactoryOutput, SliceFactoryD<TABLE_MASK>)Expand description
The factory’s wiring.
Like every RHDL kernel, this runs once per clock: it reads the current
register and child outputs (q) and the inputs, and returns this cycle’s
outputs and the next values for every register and child input (d).
It does six jobs each cycle, in the sections marked below:
| Section | What happens this cycle |
|---|---|
| time | advance the residue (0..=67) and period counters |
| key admission | at residue 0, decide key period + KEY_LEAD: real or bubble |
| decode (y − 1) | look up next cycle’s op, find its context, address the RAMs |
| issue (y) | build the BLAKE3 request of the op decoded last cycle |
| result path | register the lane’s output; route it to a RAM or an output |
| chain feed | feed chain residue of the key whose period this is |
| chain results → cache | write four positions per chain; pack chain ends |
| RAM ports | collect every RAM’s read address and write port |
Inputs: SliceFactoryInput. Outputs: SliceFactoryOutput; the
cache write appears SLICE_CHAIN_LATENCY cycles after its chain was
fed, KeyDone one cycle after the key’s parent result leaves the lane.