Module papers 

Curated primary-source reading library with implementation-oriented notes.

Reading Library

Primary sources checked 2026-10-03. These are short reading notes, not claims that the current hardware implements every method. Read in the order below.

1. The Signature Contract

Bernstein, Duif, Lange, Schwabe, Yang (2011), High-speed high-security signatures. Paper and PDF.

Introduces the Ed25519 performance/security design: compact encodings and arithmetic without secret-dependent array indices or branch conditions. Use it to understand why nonce hashing, scalar clamping, and constant-pattern selection are part of the design, not optional overhead. Its CPU performance numbers are not FPGA targets. Start here before modifying sign.rs.

RFC 8032, Edwards-Curve Digital Signature Algorithm (EdDSA). Standard and test vectors.

Use for the exact byte-level algorithm and known vectors. The core’s strict verification contract also follows the pinned Dalek implementation’s point and canonicality checks; do not replace it with a weaker equation-only test.

2. Parallel Edwards Arithmetic

Hisil, Wong, Carter, Dawson (2008), Twisted Edwards Curves Revisited. Paper.

Derives efficient extended-coordinate group operations and shows how independent products can execute on four processors. This motivates the four field multiplier lanes in a point engine. Study the dependency graph, not just the total multiplication count: independent products can share a cycle, dependent products cannot. Relevant modules: multicomb, variable_base, equation.

Explicit-Formulas Database, extended twisted Edwards coordinates. Formulas and verification scripts.

Lists formula assumptions and operation costs with symbolic-checking material. Use as a cross-check when changing coordinates. A lower multiplication count is not automatically a shorter FPGA critical path; include additions, carries, registers, and muxes. Check whether a formula requires a normalized coordinate or a particular curve constant before adopting it.

3. Fixed-Base And Compact Arithmetic

Mike Hamburg (2012), Fast and compact elliptic-curve cryptography. Paper.

Presents improved fixed-base multiplication, field arithmetic, compression, and verification methods while controlling implementation size. Read the fixed-base sections to explore comb geometry and precomputation tradeoffs. The paper discusses curves and software choices beyond Ed25519; transplanting a representation or verification shortcut requires a fresh correctness and compatibility argument. Relevant modules: multicomb_table, point_compress.

4. The Suggested FPGA Paper

Hossain et al. (2025), Low latency FPGA implementation of twisted Edward curve cryptography hardware accelerator over prime field. Author manuscript, journal DOI.

The abstract reports a unified point-operation architecture and a 164,730-cycle point multiplication at 117.8 MHz on Virtex-5. This is useful for studying resource reuse and point-operation scheduling. It is not an end-to-end million-signature-per-second result, and its point-multiplication latency cannot be compared directly to a many-context pipeline’s sustained II. Our experiment takes the parallel scheduling question further by overlapping independent messages, which is an engineering inference, not a paper claim.

5. Mapping And Measurement

AMD UG901, USE_DSP. Official synthesis documentation.

Explains arithmetic inference and USE_DSP preferences. DSP use is a mapper decision influenced by operand widths, pipeline registers, and constraints. An integer multiplication in Rust does not prove one DSP will be used.

AMD UG579, UltraScale Architecture DSP Slice User Guide. Official guide.

Documents DSP48E2’s signed 27-by-18 multiplier and its pipeline registers. Unsigned operands need a leading zero, which motivates our 26-by-17 tile. Read the multiplier and register sections before changing operand widths: using all 27 bits as an unsigned value would no longer fit the same signed primitive. The six-tile limb decomposition is this project’s engineering derivation, not a throughput claim from AMD.

AMD UG835 (2023.2), synth_design. Official command reference.

Documents out-of-context synthesis and -max_dsp. The tuner emits this ceiling and checks mapped counts afterwards. A synthesis report is not a routed frequency measurement. Maintain separate records for native simulation, generated RTL, mapping, route, and on-card execution.

Suggested Experiment Notebook

For each idea record: source paper/section, hypothesis, source fingerprint, changed modules, correctness tests, steady-state II, mapped counts, requested clock, achieved clock, and decision. Include negative results. A rejected DSP/LUT tradeoff is useful evidence for the next developer.