Expand description
Host-only, constant-memory cycle simulation without waveform recording.
RHDL’s run_fn records trace pages, which is useful for waveforms but costly
for throughput experiments. This driver uses the same Synchronous::sim
hardware transitions with tracing disabled. It is not a cryptographic model
or a replacement for RTL simulation. One CycleSim::tick is one rising edge.
Structs§
- Cycle
Sim - A native RHDL simulator with no per-cycle history allocation.