Module card 

The Ed25519 card kernel: the build’s signer behind HBM and a host port (feature card).

The problem

Every Ed25519 card number so far came from cycle simulation or from an out-of-context route. A card measurement needs one top-level kernel that Vitis can link and XRT can drive. The kernel has to be RHDL all the way down: the July card builds instantiated hand-written SystemVerilog, so they don’t count.

The idea

       AXI4-Lite (host, ap_ctrl_hs)                       HBM
             │                                        ▲        │
  ┌──────────▼────────────────────────────────────────┼────────┼──────┐
  │ registers ─seed, count, addresses─┐               │        │      │
  │    ▲ ticks, counters              ▼               │        ▼      │
  │    │        SignatureWriter ◀─ FIFO ◀─ SelectedSigner ◀─ MessageReader
  │    └─────────────────────────────────────────────────────────────┘

• Messages. One 64-byte message is one HBM beat. The reader fetches 16-beat bursts into a 64-beat FIFO, never crossing a 4 KiB page (a 4 KiB-aligned base is required).
• Signing. The build-selected SelectedSigner signs message i with tag i, under one cached key that the kernel expands from the seed argument at start.
• Signatures. The signer’s completion is a pulse with no backpressure, so completions go into a FIFO. A request is admitted only while the FIFO has room for every request in flight, so the FIFO never overflows. The writer stores signature i (R‖S, 64 bytes, one beat) at signatures + 64·i.
• Measurement. A free-running cycle counter is latched at start, when the key is cached, and when memory acknowledges the last signature.

A run signs at most 65,536 messages (the signer’s tag is 16 bits). The host runs more by starting again.

Register map (32-bit words)

Offset	Name	Access
0x00	AP_CTRL: bit 0 ap_start, 1 ap_done (clear on read), 2 ap_idle, 3 ap_ready	RW
0x04/0x08/0x0c	GIE / IER / ISR	RW
0x10/0x14	arg messages: byte address, 4 KiB aligned	W
0x18/0x1c	arg signatures: byte address, 64-byte aligned	W
0x20	arg count: 1..=65,536	W
0x28 + 4w	args seed0..seed7: the Ed25519 seed (secret, no read path)	W

Arguments sit at Vitis’s usual 8-byte steps from 0x10. | 0x100 | MAGIC = “ECD1” | R | | 0x104 | SIGNED: signatures acknowledged by memory | R | | 0x108 | FAULT: bit 0 signer, 1 read error, 2 write error, 3 bad arguments | R | | 0x110/0x114 | START_TICK lo/hi | R | | 0x118/0x11c | KEY_TICK lo/hi: the key is cached | R | | 0x120/0x124 | DONE_TICK lo/hi | R | | 0x128/0x12c | TICKS lo/hi: the live counter (reading lo snapshots hi) | R | | 0x140 + 4w | PUBLIC_KEY (8 words) | R |

Structs

AxiRead

AXI4 read master signals (kernel → memory).

AxiReadResp

AXI4 read responses (memory → kernel).

AxiWrite

AXI4 write master signals (kernel → memory): single-beat writes.

AxiWriteResp

AXI4 write responses (memory → kernel).

CardControl

The kernel’s control registers.

CardIn

Kernel inputs.

CardOut

Kernel outputs.

Ed25519Card

The Ed25519 card kernel.

LiteIn

AXI4-Lite requests from the host.

LiteOut

AXI4-Lite responses.

SigEntry

A completed signature, waiting for memory.

Constants

BURST

Beats per read burst (1 KiB).

MAGIC

“ECD1”.

MSG_FIFO_BITS

log2 of the message FIFO depth (64 beats).

SIG_FIFO_BITS

log2 of the signature FIFO depth (2,048 signatures).

Functions

ed25519_card_kernel

The kernel’s logic.

set_half

v with its low (hi false) or high 32 bits replaced by w.