pub fn reg_banks_kernel<const RA: usize, const IA: usize>(
_cr: ClockReset,
i: RegBanksIn<RA, IA>,
q: RegBanksQ<RA, IA>,
) -> (RegBanksOut, RegBanksD<RA, IA>)where
W<RA>: BitWidth,
W<IA>: BitWidth,Expand description
Wiring for RegBanks: ports pass straight through to the memories.