Expand description
Host-only, constant-memory cycle simulation without waveform recording.
RHDL’s run_fn records trace pages, which is useful for waveforms but costly
for throughput experiments. This driver uses the same Synchronous::sim
hardware transitions with tracing disabled. It is not a cryptographic model
or a replacement for RTL simulation. One CycleSim::tick is one rising edge.
§Measuring throughput
Throughput tests (sustained_* in the crate’s tests) offer a request
whenever ready is high and time the completions in the middle of the
run. The run must be several times longer than the credit pool (2,048):
a shorter run admits everything at once and measures a start-up transient
(15/11/3/1: 32.6 cycles/signature over 700 signatures, 26.43 over 6,000).
The large profiles simulate at roughly 80 cycles per second, so a steady
state run takes about 40 minutes on one core.
Structs§
- Cycle
Sim - A native RHDL simulator with no per-cycle history allocation.