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apply_powers

rhdl_fpga_planner

Function apply_powers 

Source 
pub fn apply_powers(
    mode: Mode,
    budget: &Budget,
    cx: &Context,
    slots: &mut [Slot],
    powers: Powers,
) -> ChipPlan
Expand description

Set the module powers for powers (and, in the DSig paper, the background bg) and plan the chip. Slots outside the mode get 0.

  • Ed25519 paper: the sign module gets powers.sign %, the verify module powers.verify %.
  • DSig paper: EdDSA gets B % of the budget and the HBSS foreground 100 − B; the foreground is split by powers, the background by S (Ed25519 sign) and 100 − S (Ed25519 verify).