pub const fn folded_lut(stages: u32) -> u32Expand description
Estimated LUTs of a core with a ring of stages round stages: 1,020 per
stage (round, schedule step, constant ROM, counter) plus 3,450 for the
skid buffer, the stage-0 mux and the final addition. Fitted to Yosys
synth_xilinx -family xcup of the 2-, 5- and 10-stage cores (5,491,
8,550 and 13,654 LUTs). An estimate: Yosys is not Vivado, and
nothing here is placed or timed.