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rhdl_ed25519_fast_core/
export.rs

1//! Deterministic generated-HDL export.
2//!
3//! The Rust/RHDL implementation is the only hardware source. This module
4//! compiles the complete public core into one generated Verilog netlist; it
5//! does not splice in templates, compatibility wrappers, or handwritten HDL.
6
7use anyhow::Result;
8use rhdl::prelude::*;
9
10use crate::{
11    Fast64Core,
12    field_parallel::{FieldMulPipe, Mul51Cell},
13    scalar_parallel::ScalarReducePipe,
14    sha512_parallel::Sha512Compress,
15};
16
17fn component_hdl<C>(component: C, name: &str) -> Result<String>
18where
19    C: Synchronous,
20{
21    // The explicit Icarus step in the validation gate is more predictable than
22    // RHDL's per-component probe for these large generated modules.
23    unsafe { std::env::set_var("RHDL_SKIP_IVERILOG_CHECK", "1") };
24    Ok(component.descriptor(name.into())?.hdl()?.modules.pretty())
25}
26
27/// Compile [`Fast64Core`] and return its generated Verilog netlist.
28///
29/// The returned string is a build artifact. Developers should modify the RHDL
30/// modules, regenerate the netlist, and never edit the emitted Verilog.
31pub fn fast64_core_hdl() -> Result<String> {
32    component_hdl(Fast64Core::default(), "fast64_core_rhdl")
33}
34
35/// Compile the fully pipelined radix-`2^51` field multiplier.
36pub fn field_mul_hdl() -> Result<String> {
37    component_hdl(FieldMulPipe::default(), "field_mul_rhdl")
38}
39
40/// Compile one six-stage 51-bit multiplier for inexpensive technology-mapping experiments.
41pub fn mul51_cell_hdl() -> Result<String> {
42    component_hdl(Mul51Cell::default(), "mul51_cell_rhdl")
43}
44
45/// Compile the initiation-interval-one scalar reducer.
46pub fn scalar_reduce_hdl() -> Result<String> {
47    component_hdl(ScalarReducePipe::default(), "scalar_reduce_rhdl")
48}
49
50/// Compile one iterative SHA-512 compression lane.
51pub fn sha512_compress_hdl() -> Result<String> {
52    component_hdl(Sha512Compress::default(), "sha512_compress_rhdl")
53}