rhdl_ed25519_scalable_core/ubft/
ports.rs

1//! Port types: AXI4-Stream beats and the AXI4-Lite register port (DSig's
2//! layout).
3
4use super::*;
5
6/// One 512-bit stream beat (`tvalid`, `tdata`, `tlast`; `tready` travels
7/// the other way as a plain `bool`). The layout of DSig's `Axis512`.
8#[derive(Clone, Copy, Debug, PartialEq, Digital)]
9pub struct Axis512 {
10    /// `tvalid`.
11    pub valid: bool,
12    /// `tdata`, byte 0 in bits 0..8.
13    pub data: [b8; 64],
14    /// `tlast`.
15    pub last: bool,
16}
17
18impl Axis512 {
19    /// No beat.
20    #[must_use]
21    pub fn idle() -> Self {
22        Self { valid: false, data: [b8(0); 64], last: false }
23    }
24}
25
26/// One 64-bit stream beat (the verdict stream).
27#[derive(Clone, Copy, Debug, PartialEq, Digital, Default)]
28pub struct Axis64 {
29    /// `tvalid`.
30    pub valid: bool,
31    /// `tdata`.
32    pub data: b64,
33}
34
35/// AXI4-Lite requests from the host (the layout of DSig's `AxiLiteIn`, so
36/// both services use one Verilog wrapper).
37#[derive(Clone, Copy, Debug, Default, Digital, PartialEq)]
38pub struct AxiLiteIn {
39    /// AW `valid`.
40    pub aw_valid: bool,
41    /// Write byte address (4 KiB aperture).
42    pub aw_addr: b12,
43    /// W `valid`.
44    pub w_valid: bool,
45    /// Write word.
46    pub w_data: b32,
47    /// Byte enables (ignored: every write is a whole word).
48    pub w_strb: b4,
49    /// B `ready`.
50    pub b_ready: bool,
51    /// AR `valid`.
52    pub ar_valid: bool,
53    /// Read byte address.
54    pub ar_addr: b12,
55    /// R `ready`.
56    pub r_ready: bool,
57}
58
59/// AXI4-Lite responses, every one from a register (the layout of DSig's
60/// `AxiLiteOut`).
61#[derive(Clone, Copy, Debug, Default, Digital, PartialEq)]
62pub struct AxiLiteOut {
63    /// AW `ready`.
64    pub aw_ready: bool,
65    /// W `ready`.
66    pub w_ready: bool,
67    /// B `valid`.
68    pub b_valid: bool,
69    /// B response (always OKAY).
70    pub b_resp: b2,
71    /// AR `ready`.
72    pub ar_ready: bool,
73    /// R `valid`.
74    pub r_valid: bool,
75    /// Read word.
76    pub r_data: b32,
77    /// R response (always OKAY).
78    pub r_resp: b2,
79    /// Level interrupt: `GIE && IER && ISR`.
80    pub interrupt: bool,
81}
rhdl_ed25519_scalable_core/ubft/ports.rs

rhdl_ed25519_scalable_core/ubft/
ports.rs
