rhdl_ubft/

setup.rs

//! Starting the signature service: keys in, then go.
//!
//! ubft_new derives its key pair at init with an inline Ed25519 call and
//! reads every replica's public key from `message_ptr` (8 words per
//! replica). rhdl_ubft hands both to its signature service instead.
//! [`Setup`] plays the service's host over AXI4-Lite:
//!
//! 1. the private key (`sk0..sk3`, 32 bytes) as the signer's seed,
//! 2. replica `s`'s public key into trusted key slot `s`, for every `s <
//!    node_num`, read from `message_ptr` with one burst per replica,
//! 3. the key mask (`node_num` slots), unlimited sign and verify counts,
//! 4. `ap_start`.
//!
//! The service then expands the seed and loads the keys (about 105,000
//! cycles each for Ed25519) and opens its streams. The protocol can start
//! at once: its first request waits for the stream to open.
//!
//! The register offsets are a [`ServiceMap`], so one sequencer serves the
//! Ed25519 service and DSig's.

use rhdl::prelude::*;

use crate::fetch::{FetchIn, FetchReq, Fetcher};
use crate::fetch::idle_fetch_req;
use crate::ports::{AxiLiteIn, AxiLiteOut, AxiRead, AxiReadResp, idle_lite_in};

/// Where a signature service keeps its session arguments.
#[derive(Clone, Copy, Debug, PartialEq, Digital, Default)]
pub struct ServiceMap {
    /// `ap_ctrl`.
    pub ap_ctrl: b12,
    /// Signatures this session.
    pub sign_count: b12,
    /// Verifications this session.
    pub verify_count: b12,
    /// Seed word 0 (words at +4).
    pub seed: b12,
    /// Trusted key mask.
    pub key_mask: b12,
    /// Slot 0's key word 0 (words at +4, slots at +0x20).
    pub keys: b12,
}

/// The Ed25519 uBFT service's map (`rhdl_ed25519_scalable_core::ubft`).
pub const ED25519_MAP: ServiceMap = ServiceMap {
    ap_ctrl: b12(0x000),
    sign_count: b12(0x010),
    verify_count: b12(0x014),
    seed: b12(0x050),
    key_mask: b12(0x070),
    keys: b12(0x400),
};

/// Inputs of [`Setup`].
#[derive(Clone, Copy, Debug, PartialEq, Digital, Default)]
pub struct SetupIn {
    /// Begin (one-cycle pulse).
    pub start: bool,
    /// The service's register map.
    pub map: ServiceMap,
    /// Replicas.
    pub n: b5,
    /// The private key.
    pub sk: [b64; 4],
    /// `message_ptr`.
    pub keys_base: b64,
    /// The service's AXI4-Lite answers.
    pub svc: AxiLiteOut,
    /// `message_ptr` reads.
    pub msg: AxiReadResp,
}

/// Outputs of [`Setup`].
#[derive(Clone, Copy, Debug, PartialEq, Digital, Default)]
pub struct SetupOut {
    /// Setting up.
    pub busy: bool,
    /// The service was started this cycle.
    pub done: bool,
    /// AXI4-Lite requests to the service.
    pub svc: AxiLiteIn,
    /// `message_ptr` requests.
    pub msg: AxiRead,
}

/// The sequencer's registers.
#[derive(Clone, Copy, Debug, PartialEq, Digital, Default)]
pub struct SetupState {
    /// 0 idle, 1 seed, 2 fetch a key, 3 wait for it, 4 key words, 5 mask,
    /// 6 sign count, 7 verify count, 8 start.
    pub step: b4,
    /// Word within the step (seed or key words 0..8).
    pub word: b4,
    /// Replica whose key is loading.
    pub slot: b5,
    /// The key words fetched.
    pub key: [b32; 8],
    /// A write is in flight: address and data accepted flags.
    pub aw_done: bool,
    /// Data accepted.
    pub w_done: bool,
    /// Waiting for the write response.
    pub b_wait: bool,
    /// Latched inputs.
    pub map: ServiceMap,
    /// Replicas.
    pub n: b5,
    /// The private key.
    pub sk: [b64; 4],
    /// `message_ptr`.
    pub keys_base: b64,
}

/// Service setup sequencer (see the module docs).
#[derive(Clone, Debug, Synchronous, SynchronousDQ)]
pub struct Setup {
    state: rhdl_fpga::core::dff::DFF<SetupState>,
    fetch: Fetcher,
}

impl Default for Setup {
    fn default() -> Self {
        Self { state: rhdl_fpga::core::dff::DFF::new(SetupState::default()), fetch: Fetcher::default() }
    }
}

impl SynchronousIO for Setup {
    type I = SetupIn;
    type O = SetupOut;
    type Kernel = setup_kernel;
}

/// The sequencer's logic.
#[kernel]
pub fn setup_kernel(_cr: ClockReset, i: SetupIn, q: SetupQ) -> (SetupOut, SetupD) {
    let r = q.state;
    let mut s = r;
    let mut o = SetupOut { busy: false, done: false, svc: idle_lite_in(), msg: q.fetch.axi };
    let mut f = FetchIn { req: idle_fetch_req(), axi: i.msg };
    f.axi = i.msg;
    o.msg = q.fetch.axi;
    o.busy = r.step != b4(0);
    if r.step == b4(0) && i.start {
        s.step = b4(1);
        s.word = b4(0);
        s.slot = b5(0);
        s.map = i.map;
        s.n = i.n;
        s.sk = i.sk;
        s.keys_base = i.keys_base;
    }
    // The register write of this step, if it has one.
    let mut write = false;
    let mut addr = b12(0);
    let mut data = b32(0);
    if r.step == b4(1) {
        write = true;
        addr = r.map.seed + (r.word.resize::<12>() << b12(2));
        let mut w = r.sk[0];
        for k in 0..4 {
            if (r.word >> b4(1)) == b4(k as u128) {
                w = r.sk[k];
            }
        }
        data = if (r.word & b4(1)) == b4(1) { (w >> b64(32)).resize() } else { w.resize() };
    }
    if r.step == b4(2) {
        f.req = FetchReq { start: true, base: r.keys_base, word: r.slot.resize::<32>() << b32(3), count: b6(8) };
        if !q.fetch.busy {
            s.step = b4(3);
        }
    }
    if r.step == b4(3) && q.fetch.done {
        for k in 0..8 {
            s.key[k] = q.fetch.words[k];
        }
        s.word = b4(0);
        s.step = b4(4);
    }
    if r.step == b4(4) {
        write = true;
        addr = r.map.keys + (r.slot.resize::<12>() << b12(5)) + (r.word.resize::<12>() << b12(2));
        let mut w = b32(0);
        for k in 0..8 {
            if r.word == b4(k as u128) {
                w = r.key[k];
            }
        }
        data = w;
    }
    if r.step == b4(5) {
        write = true;
        addr = r.map.key_mask;
        data = (b32(1) << r.n.resize::<32>()) - b32(1);
    }
    if r.step == b4(6) {
        write = true;
        addr = r.map.sign_count;
        data = !b32(0);
    }
    if r.step == b4(7) {
        write = true;
        addr = r.map.verify_count;
        data = !b32(0);
    }
    if r.step == b4(8) {
        write = true;
        addr = r.map.ap_ctrl;
        data = b32(1);
    }
    // One AXI4-Lite write: address and data, then the response.
    let mut wrote = false;
    if write && !r.b_wait {
        o.svc.aw_valid = !r.aw_done;
        o.svc.aw_addr = addr;
        o.svc.w_valid = !r.w_done;
        o.svc.w_data = data;
        o.svc.w_strb = b4(0xf);
        let aw = r.aw_done || i.svc.aw_ready;
        let w = r.w_done || i.svc.w_ready;
        s.aw_done = aw;
        s.w_done = w;
        if aw && w {
            s.b_wait = true;
        }
    }
    if r.b_wait {
        o.svc.b_ready = true;
        if i.svc.b_valid {
            s.b_wait = false;
            s.aw_done = false;
            s.w_done = false;
            wrote = true;
        }
    }
    if wrote {
        // Advance to the next write.
        if r.step == b4(1) {
            s.word = r.word + b4(1);
            if r.word == b4(7) {
                s.step = b4(2);
            }
        }
        if r.step == b4(4) {
            s.word = r.word + b4(1);
            if r.word == b4(7) {
                s.slot = r.slot + b5(1);
                s.step = if r.slot + b5(1) == r.n { b4(5) } else { b4(2) };
            }
        }
        if r.step == b4(5) {
            s.step = b4(6);
        }
        if r.step == b4(6) {
            s.step = b4(7);
        }
        if r.step == b4(7) {
            s.step = b4(8);
        }
        if r.step == b4(8) {
            s.step = b4(0);
            o.done = true;
        }
    }
    (o, SetupD { state: s, fetch: f })
}