Struct DualTableRom 

pub struct DualTableRom { /* private fields */ }

Two registered T0 lookups per cycle from one true dual-port ROM.

Why this is a hand-written RHDL primitive

A block RAM tile on the U280 (a BRAM18) has two independent read ports. RHDL’s own SyncBRAM exposes only one of them, so the first version of this type was two SyncBRAMs holding the same table: one BRAM18 per lookup. Build v4 (four slices, T-tables in rounds 3–8) needed 4,033 BRAM18 sites in the kernel region, which has 3,552, and failed placement. Serving both lookups from one memory halves that: a table round needs 32 BRAM18s instead of 64.

RHDL builds its memories the same way this type does: SyncBRAM is a Rust simulation model plus a Verilog template, registered with RHDL as a netlist primitive. DualTableRom follows that recipe exactly (compare rhdl_fpga::core::ram::synchronous), with a second read port and no write port. Nothing about it is opaque: the simulation model below is ten lines, the Verilog is printed in full by DualTableRom::hdl, and the tests in tests/chain_step.rs check every table round against the AES reference.

Timing

Addresses presented in cycle t give their words in cycle t + 1, on both ports, exactly like the two-ROM version it replaces. The output before the first clock edge is unspecified; ownership lives in the enclosing pipeline’s valid bits. Reset is ignored: a ROM has no state.

           ┌──────────── one BRAM18 (ram_style = "block") ────────────┐
 a ──────▶ │ port A: o_a <= T0[a]       256 × 32 T0, preloaded        │ ──▶ o.a
 b ──────▶ │ port B: o_b <= T0[b]       by the bitstream              │ ──▶ o.b
           └──────────────────────────────────────────────────────────┘

Trait Implementations

impl Clone for DualTableRom

fn clone(&self) -> DualTableRom

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for DualTableRom

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for DualTableRom

The ROM holds T0.

fn default() -> Self

Returns the “default value” for a type.

impl Synchronous for DualTableRom

Behaviour (simulation) and structure (Verilog) of the dual-port ROM.

type S = DualTableRomState

Two output registers, modelled by [DualTableRomState].

fn init(&self) -> Self::S

Power-up output is “don’t care”, like the RAM’s output register.

fn sim( &self, clock_reset: ClockReset, input: Self::I, state: &mut Self::S, ) -> Self::O

One half-clock step: look both addresses up while the clock is low, capture on the rising edge, always show the captured words.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Register the Verilog below with RHDL as a primitive, the same way SyncBRAM does.

fn children( &self, _parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

impl SynchronousDQ for DualTableRom

A primitive has no child circuits, so no D/Q wiring.

type D = ()

The type of the internal data input to the children of the circuit.

type Q = ()

The type of the internal data output from the children of the circuit.

impl SynchronousIO for DualTableRom

Ports of DualTableRom: two addresses in, two table words out.

type I = TableRead

Two 8-bit addresses per cycle.

type O = TableWords

The two 32-bit T0 words, one cycle later.

type Kernel = NoSynchronousKernel<ClockReset, TableRead, (), (TableWords, ())>

No RHDL kernel: the behaviour is the hand-written sim and hdl.