Struct RoundPipeline 

pub struct RoundPipeline<const STAGES: usize>
where
    W<STAGES>: BitWidth,
{ /* private fields */ }

Registered prefix of the BLAKE3 compression pipeline.

Only STAGES = 28 produces complete BLAKE3 output. Smaller specializations exist for bounded lowering and RTL-equivalence tests; they return XORs of incomplete working states and must not be used as a hash. The complete specialization is CompressionPipeline.

The initiation interval is one cycle, with STAGES registered transfers of latency. Data and tags do not reset. Synchronous reset clears all valid bits and therefore flushes every in-flight token.

  stage 0        stage 1    stage 2    stage 3          stage 27
  init+phase 0 ─▶ phase 1 ─▶ phase 2 ─▶ phase 3 ─▶ ... ─▶ phase 3 ─▶ feed_forward ─▶ output
  (reg)           (reg)      (reg)      (reg)            (reg)      (no register)

  tag, valid: copied one stage per clock beside the data

#[rhdl(dq_no_prefix)] names the generated input/output bundles plain D and Q (instead of RoundPipelineD/RoundPipelineQ); the kernel below uses those names.

Trait Implementations

impl<const STAGES: usize> Clone for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

fn clone(&self) -> RoundPipeline<STAGES>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const STAGES: usize> Debug for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const STAGES: usize> Default for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

Build a pipeline of STAGES stages, checking that STAGES is legal.

fn default() -> Self

Data registers start as “don’t care”; every valid bit starts false.

Panics

Panics if STAGES is 0 or more than 28.

impl<const STAGES: usize> Synchronous for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

type S = (<RoundPipeline<STAGES> as SynchronousDQ>::Q, <[DFF<RoundState>; STAGES] as Synchronous>::S, <[DFF<Bits<32>>; STAGES] as Synchronous>::S, <[DFF<bool>; STAGES] as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl<const STAGES: usize> SynchronousDQ for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

type Q = Q<STAGES>

The type of the internal data output from the children of the circuit.

type D = D<STAGES>

The type of the internal data input to the children of the circuit.

impl<const STAGES: usize> SynchronousIO for RoundPipeline<STAGES>

where W<STAGES>: BitWidth,

Ports of RoundPipeline: one request in, one result out per clock.

type I = CompressionInput

A compression request.

type O = CompressionOutput

Its result, STAGES clocks later.

type Kernel = round_pipeline_kernel<STAGES>

The stage wiring below.