Function cache_bank_kernel 

pub fn cache_bank_kernel(
    _clock_reset: ClockReset,
    input: In<[b8; 18], 16>,
    q: CacheBankQ,
) -> ([b8; 18], CacheBankD)

Route each row to its half; delay both halves’ data and the “which half” bit equally; select at the end.

• input: this cycle’s read address and optional write (16-bit rows, 18-byte value). It is only registered here; it takes effect next cycle.
• q: the current register and RAM outputs.
• Returns the 18-byte node for the address presented CACHE_READ_LATENCY cycles ago, and the next register/RAM inputs.

The write goes to exactly one half (bit 15 picks it), so a row is never stored twice. Reads go to both halves at once; the mux discards the wrong one at the end.