Function chain_step_kernel 

pub fn chain_step_kernel(
    clock_reset: ClockReset,
    input: ChainStepInput,
    q: ChainStepLaneQ,
) -> (ChainStepOutput, ChainStepLaneD)

Stage wiring for ChainStepLane.

Inputs: clock_reset, the new request input, and q (every child’s current output). Outputs: the ChainStepOutput leaving stage 19 and d (every child’s next input). Per AES round r:

• S-box stage r reads mixed[r - 1] (or the new block for r = 0), with the constant bytes pinned;
• mixed[r] reads S-box stage r’s output, pinned again, through MixColumns + AddRoundKey (+ word mix when r is odd).

Every loop bound and index is a constant, so RHDL unrolls all of it into fixed wiring.