Struct ChainStepLane 

pub struct ChainStepLane { /* private fields */ }

Twenty-stage, II = 1 DSig chain step with compile-time constant folding.

Each AES round r is two registered half-rounds:

 mixed[r-1] ─pin─▶ SboxStage subs[r] ─pin─▶ MixColumns+key(+word mix) ─▶ mixed[r]
                 (S-box table, reg)                                     (reg)

SboxStages keeps the generated netlist compact. The pin steps apply KNOWN: registers that only ever hold constants, or that never reach an output, have no loads, and synthesis removes them.

The whole lane, stage by stage (S = S-box stage register, M = mixed register; both are 64 bytes wide):

  block ─▶ S0 ─▶ M0 ─▶ S1 ─▶ M1 ─▶ S2 ─▶ ... ─▶ S9 ─▶ M9 ─▶ digest ─▶ node
  stage:   0     1     2     3     4            18    19
                             +MIX                     +MIX
  side band:  feed_forward (18 B), tag (32 bit), valid — 20 registers each

Timing contract: one token per clock in, the result exactly 20 clocks later, no backpressure. The S-box register S lives inside SboxStages (a ROM’s registered read); the M registers are mixed.

Trait Implementations

impl Clone for ChainStepLane

fn clone(&self) -> ChainStepLane

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ChainStepLane

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ChainStepLane

Build a lane with S-boxes placed as crate::sbox_placement decided.

fn default() -> Self

Data registers start as “don’t care”; every valid bit starts false.

impl Synchronous for ChainStepLane

type S = (<ChainStepLane as SynchronousDQ>::Q, <SboxStages as Synchronous>::S, <SboxLoader as Synchronous>::S, <[DFF<[Bits<8>; 64]>; 10] as Synchronous>::S, <[DFF<[Bits<8>; 18]>; 20] as Synchronous>::S, <[DFF<Bits<32>>; 20] as Synchronous>::S, <[DFF<bool>; 20] as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl SynchronousDQ for ChainStepLane

type Q = ChainStepLaneQ

The type of the internal data output from the children of the circuit.

type D = ChainStepLaneD

The type of the internal data input to the children of the circuit.

impl SynchronousIO for ChainStepLane

Ports of ChainStepLane: one chain step in, one node out per clock.

type I = ChainStepInput

Salted nonce, node, tag and valid.

type O = ChainStepOutput

Next node, tag, valid and ready, 20 clocks later.

type Kernel = chain_step_kernel

The stage wiring below.