Struct HarakaPipeline 

pub struct HarakaPipeline<const STAGES: usize> { /* private fields */ }

Prefix of the twenty-stage Haraka pipeline, for bounded validation.

STAGES must be between one and twenty inclusive. Only the full twenty stages implement Haraka-512. Shorter instances expose the truncated, feed-forwarded intermediate state for focused equivalence tests; they must never be used as a cryptographic hash. Every specialization accepts one token per cycle without backpressure and delays validity by STAGES registered transfers. Reset flushes every in-flight token.

Four parallel shift registers, all STAGES deep, move in lock step:

  input ─▶ [stage 0] ─▶ [stage 1] ─▶ ... ─▶ [stage STAGES-1] ─▶ digest
  state:    sub/shift    mix/key             (computed)
  feed_forward, tag, valid: copied unchanged from stage to stage

Only valid has a reset value. The data registers do not, which keeps them cheap (no reset fan-out) and is safe because nothing reads data whose valid is false.

Trait Implementations

impl<const STAGES: usize> Clone for HarakaPipeline<STAGES>

fn clone(&self) -> HarakaPipeline<STAGES>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const STAGES: usize> Debug for HarakaPipeline<STAGES>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const STAGES: usize> Default for HarakaPipeline<STAGES>

Build a pipeline of STAGES stages, checking that STAGES is legal.

fn default() -> Self

Data registers start as “don’t care”; every valid bit starts false.

Panics

Panics if STAGES is outside 1..=20.

impl<const STAGES: usize> Synchronous for HarakaPipeline<STAGES>

type S = (<HarakaPipeline<STAGES> as SynchronousDQ>::Q, <[DFF<[Bits<8>; 64]>; STAGES] as Synchronous>::S, <[DFF<[Bits<8>; 32]>; STAGES] as Synchronous>::S, <[DFF<Bits<32>>; STAGES] as Synchronous>::S, <[DFF<bool>; STAGES] as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl<const STAGES: usize> SynchronousDQ for HarakaPipeline<STAGES>

type Q = HarakaPipelineQ<STAGES>

The type of the internal data output from the children of the circuit.

type D = HarakaPipelineD<STAGES>

The type of the internal data input to the children of the circuit.

impl<const STAGES: usize> SynchronousIO for HarakaPipeline<STAGES>

Ports of HarakaPipeline: one block in, one digest out per clock.

type I = HarakaInput

A block, a tag and a valid bit.

type O = HarakaOutput

A digest, the same tag and a valid bit, STAGES clocks later.

type Kernel = haraka_pipeline_kernel<STAGES>

The stage wiring below.