Struct ContextRams 

pub struct ContextRams { /* private fields */ }

The six small per-key context RAMs, grouped into one child.

RHDL’s Synchronous derive stores child state in a tuple, and Rust only compares tuples of up to twelve elements, so a parent can have at most eleven direct children. Grouping these LUT RAMs keeps the factory legal.

Each RAM has CONTEXTS entries, one per key context, a registered read (data appears the cycle after the address) and one write port.

Trait Implementations

impl Clone for ContextRams

fn clone(&self) -> ContextRams

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ContextRams

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for ContextRams

Six empty RAMs; their contents are don’t-care until written.

fn default() -> Self

Builds the six RAMs with default (unloaded) contents.

impl Synchronous for ContextRams

type S = (<ContextRams as SynchronousDQ>::Q, <SyncBRAM<[Bits<32>; 8], CTX_BITS> as Synchronous>::S, <SyncBRAM<[Bits<8>; 16], CTX_BITS> as Synchronous>::S, <SyncBRAM<[Bits<8>; 16], CTX_BITS> as Synchronous>::S, <SyncBRAM<[Bits<8>; 16], CTX_BITS> as Synchronous>::S, <SyncBRAM<[Bits<32>; 8], CTX_BITS> as Synchronous>::S, <SyncBRAM<[Bits<32>; 8], CTX_BITS> as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl SynchronousDQ for ContextRams

type Q = ContextRamsQ

The type of the internal data output from the children of the circuit.

type D = ContextRamsD

The type of the internal data input to the children of the circuit.

impl SynchronousIO for ContextRams

Connects ContextRams to its port types and wiring kernel.

type I = ContextRamsIn

All six RAMs’ read addresses and write ports.

type O = ContextRamsOut

All six RAMs’ registered read data.

type Kernel = context_rams_kernel

The pass-through wiring.