Module export 

Verilog export of the build-selected profile and of single blocks.

The profile is a build-time constant, ED25519_SCALABLE_PROFILE = fb,sha,sc,compress (default 15,11,3,1); build.rs turns it into SelectedSigner, so only that size is generated. Output goes to generated/; it is an output for synthesis only and is never edited or read back as a source.

cargo run --profile sim --bin export_scalable                  # the profile
cargo run --profile sim --bin export_scalable -- --small       # Ed25519SignCoreSmall
cargo run --profile sim --bin export_scalable -- --block fb_machine

Lowering memory

Stock RHDL builds, besides the hierarchical HDL, a flattened bit-level netlist at every level of the hierarchy and keeps every compiled kernel, so memory grows with the number of instances: 15/11/3/1 needed more than 6 GiB. The vendored rhdl-core carries a local patch (patches/rhdl-hdl-only-export-20261014.diff): with RHDL_HDL_ONLY=1 only the HDL is built. Every export in this module sets it unless RHDL_KEEP_NETLIST is set.

Export	Stock	HDL only
Ed25519SignCore	3.50 GB, 99 s	190 MB, 11 s, byte-identical output
15/11/3/1	> 6 GiB (out of memory)	1.75 GB, 72 s, 36.8 MB of Verilog

Constants

BLOCKS

Names accepted by block_hdl, in the order export_scalable --blocks writes them.

PROFILE

Signer profile selected by ED25519_SCALABLE_PROFILE at build time (a SHA count of 0 means the shared line).

VERIFY_PROFILE

Verifier profile selected by ED25519_VERIFY_PROFILE at build time.

Functions

block_hdl

Verilog of one leaf block, exported for mapping calibration (the Yosys leaf maps behind config::yosys_calibrated). name is one of BLOCKS and is also used as the top module name and file stem; any other name is an error.

selected_signer_hdl

Verilog of the build-selected signer profile (SelectedSigner, set by ED25519_SCALABLE_PROFILE at build time), top module scalable_sign_core.

selected_verifier_hdl

Verilog of the build-selected verifier (SelectedVerifier, set by ED25519_VERIFY_PROFILE at build time), top module known_key_verify_core.

small_signer_hdl

Verilog of Ed25519SignCoreSmall (CachedSignIn/CachedSignOut ports, every module prefixed ed25519_sign_core).

ubft_hdl

Verilog of the uBFT service UbftEd25519<1, 1> (feature ubft), top module ubft_ed25519.

Type Aliases

SelectedSigner

The selected signer type.

SelectedVerifier

The selected verifier type.