Struct KnownKeyVerifyCore 

pub struct KnownKeyVerifyCore<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> { /* private fields */ }

Known-key strict verifier with NV verify machines, NSHA SHA-512 rings and NSC scalar rings; with SH = 1 it hashes through the shared SHA-512 port (VerifyOut::sha_ext) instead and its rings stay idle (use NSHA = 1; synthesis removes an idle ring).

Limits (checked in Default): 1 <= NV <= 64, NSHA >= 1, NSC >= 1, SH <= 1.

Trait Implementations

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> Clone for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

fn clone(&self) -> KnownKeyVerifyCore<NV, NSHA, NSC, SH>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> Debug for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> Default for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

Reset state: all slots empty, all 2,048 contexts free, full compress credits, every verify-machine context free.

fn default() -> Self

Builds the reset state.

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> Synchronous for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

type S = (<KnownKeyVerifyCore<NV, NSHA, NSC, SH> as SynchronousDQ>::Q, <DFF<VerifyRegs<NV>> as Synchronous>::S, <VerifyMems as Synchronous>::S, <[FieldMachine<5, 32, 9, 5, 10, 9, KEY_TABLE_BITS>; NV] as Synchronous>::S, <[ShaRing; NSHA] as Synchronous>::S, <[ScalarRing; NSC] as Synchronous>::S, <CompressStage as Synchronous>::S, <FieldMachine<5, 32, 11, 9, 12, 1, 1> as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> SynchronousDQ for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

type Q = Q<NV, NSHA, NSC, SH>

The type of the internal data output from the children of the circuit.

type D = D<NV, NSHA, NSC, SH>

The type of the internal data input to the children of the circuit.

impl<const NV: usize, const NSHA: usize, const NSC: usize, const SH: usize> SynchronousIO for KnownKeyVerifyCore<NV, NSHA, NSC, SH>

Ports and kernel of KnownKeyVerifyCore.

type I = VerifyIn

Input port bundle.

type O = VerifyOut

Output port bundle.

type Kernel = known_key_verify_kernel<NV, NSHA, NSC, SH>

Kernel computing the outputs and the next state.