Struct SboxPair 

pub struct SboxPair { /* private fields */ }

Two registered S-box lookups per cycle from one dual-port memory.

Why pairs

A block RAM tile (BRAM18) and an UltraRAM each have two ports, but RHDL’s SyncBRAM uses only one. Built from SyncBRAMs, every S-box placed in RAM cost a whole BRAM18 or URAM, so four slices could not afford to move their leftover S-boxes (rounds 0–2 and 9 of a T-table lane) out of LUTs: build v5 still spent 17,040 LUT-RAM per slice on them. A pair serves two S-boxes of the same round from one memory, halving the RAM per box, the same step DualTableRom took for T-tables.

           ┌──────── one memory (style: LUT, block or ultra) ────────┐
 a ──────▶ │ port A: o_a <= S[a]   (UltraRAM: or write the loader's   │ ──▶ o.a
           │                        entry while loading)               │
 b ──────▶ │ port B: o_b <= S[b]                                      │ ──▶ o.b
           └──────────────────────────────────────────────────────────┘

Timing

Addresses in cycle t give their bytes in cycle t + 1 on both ports, like a SyncBRAM ROM. Reset is ignored: ownership lives in the lane’s valid bits, and an UltraRAM pair’s lane reports “not ready” until its loader has written all 256 entries. While loading, port A does the write (its read output is meaningless then), so the memory never needs more than the two ports UltraRAM has.

Like DualTableRom this is a hand-specified RHDL primitive: a Rust simulation model plus the Verilog printed by SboxPair::hdl, checked against each other in Icarus by the tests below.

Implementations

impl SboxPair

pub fn new(style: PairStyle) -> Self

A pair built from style memory.

Trait Implementations

impl Clone for SboxPair

fn clone(&self) -> SboxPair

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for SboxPair

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Synchronous for SboxPair

Behaviour (simulation) and structure (Verilog) of the pair.

type S = SboxPairState

Memory contents and the two output registers.

fn init(&self) -> Self::S

A ROM starts holding the S-box; an UltraRAM starts empty (zeros here, unknown on the chip). Outputs start as “don’t care”.

fn sim( &self, clock_reset: ClockReset, input: Self::I, state: &mut Self::S, ) -> Self::O

One half-clock step: read both addresses while the clock is low, capture (and, for UltraRAM, write) on the rising edge.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Register the Verilog below with RHDL as a primitive.

fn children( &self, _parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

impl SynchronousDQ for SboxPair

A primitive has no child circuits, so no D/Q wiring.

type D = ()

The type of the internal data input to the children of the circuit.

type Q = ()

The type of the internal data output from the children of the circuit.

impl SynchronousIO for SboxPair

Ports of SboxPair.

type I = PairRead

Two addresses and the loader’s write.

type O = PairBytes

The two substituted bytes, one cycle later.

type Kernel = NoSynchronousKernel<ClockReset, PairRead, (), (PairBytes, ())>

No RHDL kernel: the behaviour is the hand-written sim and hdl.