Module axi4 

Packed 512-bit AXI4 memory-master channels for the U280 HBM ports.

The problem

The signer lives on an FPGA card, but its inputs (messages) and outputs (signature frames) live in HBM, the card’s stacked high-bandwidth DRAM. The only way an RTL kernel reaches HBM is through AXI4, the standard ARM bus protocol that Vitis (the AMD/Xilinx tool that links kernels into a card image) speaks. The host CPU, in turn, talks to the kernel through AXI4-Lite, a cut-down AXI with one 32-bit word per transfer and no bursts. This module defines those signals as plain RHDL structs so the rest of the crate can drive them like any other wires.

The idea: valid/ready handshakes

Every AXI channel is one-way and carries a valid from the sender and a ready from the receiver. A transfer happens on the clock edge where both are high. Neither side may wait for the other before raising its own signal in a way that could deadlock, and a sender must hold its data steady until the transfer happens.

  AXI4 write (kernel → HBM), used by hbm_writer
    AW  kernel ──awvalid, awaddr, awlen──▶ memory   ◀── awready
    W   kernel ──wvalid, wdata, wlast────▶ memory   ◀── wready
    B   kernel ◀──bvalid, bresp────────── memory   ──▶ bready

  AXI4 read (HBM → kernel), used by msg_reader
    AR  kernel ──arvalid, araddr, arlen──▶ memory   ◀── arready
    R   kernel ◀──rvalid, rdata, rlast─── memory   ──▶ rready

  AXI4-Lite (host → kernel registers), used by engine
    AW, W, B, AR, R as above, 32-bit data, one word per transfer

The decision: model only what we drive

Vitis connects each m_axi port of an RTL kernel to an HBM pseudo-channel. Only the signals the DSig masters drive are modelled; every other AXI field is tied to its canonical value in the Verilog wrapper. Field order matches the packed layout the wrapper slices, so renaming a field is an ABI change. (ABI, “application binary interface”, here means the exact bit layout the generated Verilog wrapper expects.)

Burst rules the masters obey (AXI4, §A3.4): 64-byte beats (size = 6), incrementing bursts, at most 256 beats, and no burst crosses a 4 KiB boundary. DSig frames are 26 beats placed on a 2 KiB stride, and message reads are 16-beat (1 KiB) bursts from a 4 KiB-aligned base, so every burst is legal by construction.

A beat is one data transfer on the W or R channel (64 bytes here). A burst is a run of beats that shares one address; awlen/arlen hold the beat count minus one, so 0 means one beat and 25 means 26 beats.

Where to go next

crate::hbm_writer drives WriteRequest and reads WriteResponse; crate::msg_reader drives ReadRequest and reads ReadResponse; crate::engine serves AxiLiteIn and answers with AxiLiteOut.

Structs

AxiLiteIn

Named-port-compatible input; every field is one AXI-Lite channel signal.

AxiLiteOut

Stable response channels plus the optional level interrupt.

ReadRequest

Kernel-to-memory signals of a read-only master (the outputs of crate::msg_reader::MessageReader).

ReadResponse

Memory-to-kernel signals of a read-only master (the inputs of crate::msg_reader::MessageReader).

WriteRequest

Kernel-to-memory signals of a write-only master (the outputs of crate::hbm_writer::HbmWriter).

WriteResponse

Memory-to-kernel signals of a write-only master (the inputs of crate::hbm_writer::HbmWriter).

Constants

RESP_OKAY

Response code for success (OKAY, 2 bits, value 0).