Struct AxiLiteIn 

pub struct AxiLiteIn {
    pub aw_valid: bool,
    pub aw_addr: b12,
    pub w_valid: bool,
    pub w_data: b32,
    pub w_strb: b4,
    pub b_ready: bool,
    pub ar_valid: bool,
    pub ar_addr: b12,
    pub r_ready: bool,
}

Named-port-compatible input; every field is one AXI-Lite channel signal.

“Named-port-compatible” means the field names map one-to-one onto the s_axi_control_* ports Vitis expects, so the Verilog wrapper can connect them by name.

Fields

aw_valid: bool

Write address validity (AW valid, 1 bit).

aw_addr: b12

Byte address in the 4 KiB aperture (12 bits, so 0x000..0xfff).

w_valid: bool

Write data validity (W valid, 1 bit).

w_data: b32

Write word, little-endian byte lanes (32 bits).

w_strb: b4

One enable per write byte (4 bits). The DSig register file treats every write as a whole 32-bit word and ignores this field.

b_ready: bool

Host accepts a write response (B ready, 1 bit).

ar_valid: bool

Read address validity (AR valid, 1 bit).

ar_addr: b12

Read byte address (12 bits).

r_ready: bool

Host accepts a read response (R ready, 1 bit).

Trait Implementations

impl Clone for AxiLiteIn

fn clone(&self) -> AxiLiteIn

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for AxiLiteIn

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for AxiLiteIn

fn default() -> AxiLiteIn

Returns the “default value” for a type.

impl Digital for AxiLiteIn

const BITS: usize

Associated constant that gives the total number of bits needed to represent the value.

fn static_kind() -> Kind

Returns the [Kind] (run time type descriptor) of the value as a static method

fn bin(self) -> Box<[BitX]>

Returns the binary representation of the value as a vector of [BitX].

fn dont_care() -> Self

Returns a “don’t care” value for the type.

fn bits() -> usize

Returns the number of bits needed to represent the value.

fn kind(&self) -> Kind

Returns the [Kind] (run time type descriptor) of the value.

fn typed_bits(self) -> TypedBits

Returns the value as a [TypedBits], which includes both the bits and the kind.

fn discriminant(self) -> TypedBits

Returns the discriminant of the value as a [TypedBits].

fn variant_kind(self) -> Kind

Returns the [Kind] of the variant if the value is an enum with variants.

fn binary_string(self) -> String

Returns the binary representation of the value as a string of ‘0’, ‘1’, and ‘X’.

impl PartialEq for AxiLiteIn

fn eq(&self, other: &AxiLiteIn) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for AxiLiteIn

impl Eq for AxiLiteIn

impl StructuralPartialEq for AxiLiteIn