pub fn table_chain_step_kernel<const TABLE_MASK: usize>(
clock_reset: ClockReset,
input: ChainStepInput,
q: TableChainStepLaneQ<TABLE_MASK>,
) -> (ChainStepOutput, TableChainStepLaneD<TABLE_MASK>)Expand description
Stage wiring for TableChainStepLane.
Inputs and outputs as chain_step_kernel. First it wires every round
the LUT way, exactly like chain_step_kernel. Then, for each table
round selected by TABLE_MASK, it overrides that round: the S-box stage
gets zeros, the ROMs get the (pinned) state, and mixed[r] takes the
table result. Both paths have one register (S-box ROM or table ROM)
followed by one mixed register, so latency stays 20.