Struct TableChainStepLane 

pub struct TableChainStepLane<const TABLE_MASK: usize> { /* private fields */ }

ChainStepLane with selected AES rounds moved from LUTs into T-table ROMs.

Bit r of TABLE_MASK moves AES round r (0-based) into DualTableRoms. Only rounds 3–8 are allowed: there KNOWN proves nothing constant and every output byte is needed, so a table never replaces logic synthesis would have deleted anyway. Each table round uses 32 ROMs, normally 32 BRAM18s.

A precision note: by the same backward analysis as LIVE_SBOX, rounds 7 and 8 each have 16 positions that cannot reach the output (see the per-round table in the module docs). In those rounds the ROM pairs for the unobserved positions have no loads and are removed like the S-boxes they replace, so the table still never pays for deleted work; it just uses fewer ROMs than 32.

 LUT round:    mixed[r-1] ─▶ SboxStage (reg) ─▶ MixColumns+key (LUT) ─▶ mixed[r]
 table round:  mixed[r-1] ─▶ 32 × ROM  (reg) ─▶ 4-way XOR+key (LUT) ─▶ mixed[r]

Latency, II and tag behaviour equal ChainStepLane; the tests check several masks against the same reference.

Why offer this at all: block RAM is a separate budget from LUTs. Moving a round into tables trades LUTs (the binding limit) for block RAMs that would otherwise sit unused. TABLE_MASK = 0 is exactly ChainStepLane. This is the lane type the Haraka profile instantiates (see crate::chain_lane).

Every round keeps both a LUT path and, if it is a table slot, a table path in the source. The constant TABLE_MASK picks one per round, and synthesis deletes the other: unused ROMs have no loads, and an S-box stage fed with zeros folds to constants.

Trait Implementations

impl<const TABLE_MASK: usize> Clone for TableChainStepLane<TABLE_MASK>

fn clone(&self) -> TableChainStepLane<TABLE_MASK>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const TABLE_MASK: usize> Debug for TableChainStepLane<TABLE_MASK>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const TABLE_MASK: usize> Default for TableChainStepLane<TABLE_MASK>

Build a lane, rejecting masks outside rounds 3..=8.

fn default() -> Self

Data registers start as “don’t care”; every valid bit starts false.

Panics

Panics if TABLE_MASK sets a bit outside rounds 3..=8.

impl<const TABLE_MASK: usize> Synchronous for TableChainStepLane<TABLE_MASK>

type S = (<TableChainStepLane<TABLE_MASK> as SynchronousDQ>::Q, <SboxStages as Synchronous>::S, <SboxLoader as Synchronous>::S, <[[DualTableRom; 32]; 6] as Synchronous>::S, <[DFF<[Bits<8>; 64]>; 10] as Synchronous>::S, <[DFF<[Bits<8>; 18]>; 20] as Synchronous>::S, <[DFF<Bits<32>>; 20] as Synchronous>::S, <[DFF<bool>; 20] as Synchronous>::S)

The simulation state type. This type is used to represent the internal state of the circuit during simulation. It must be PartialEq and Clone. It holds whatever state is needed to compute the output of the circuit given it’s input. This state is typically auto-derived by the Synchronous derive macro, and it’s typically a struct containing the states of all the subcircuits, along with their last know outputs.

fn init(&self) -> Self::S

Initialize the simulation state. This method returns the initial state of the circuit for simulation. This is typically auto-derived by the Synchronous derive macro, and it typically initializes the states of all the subcircuits to their initial states.

fn children( &self, parent_scope: &ScopedName, ) -> impl Iterator<Item = Result<Descriptor<SyncKind>, RHDLError>>

Iterate over the child circuits of this circuit.

fn sim( &self, clock_reset: ClockReset, input: <Self as SynchronousIO>::I, state: &mut Self::S, ) -> <Self as SynchronousIO>::O

Simulate the circuit given it’s input, clock reset, and current state.

fn descriptor( &self, scoped_name: ScopedName, ) -> Result<Descriptor<SyncKind>, RHDLError>

Provides run time reflection of the circuit.

impl<const TABLE_MASK: usize> SynchronousDQ for TableChainStepLane<TABLE_MASK>

type Q = TableChainStepLaneQ<TABLE_MASK>

The type of the internal data output from the children of the circuit.

type D = TableChainStepLaneD<TABLE_MASK>

The type of the internal data input to the children of the circuit.

impl<const TABLE_MASK: usize> SynchronousIO for TableChainStepLane<TABLE_MASK>

Same ports as ChainStepLane.

type I = ChainStepInput

Salted nonce, node, tag and valid.

type O = ChainStepOutput

Next node, tag, valid and ready, 20 clocks later.

type Kernel = table_chain_step_kernel<TABLE_MASK>

The stage wiring below.