Module export 

Deterministic generated-HDL export.

The Rust/RHDL implementation is the only hardware source. This module compiles the complete public core into one generated Verilog netlist; it does not splice in templates, compatibility wrappers, or handwritten HDL.

Functions

fast64_core_hdl

Compile Fast64Core and return its generated Verilog netlist.

field_mul_hdl

Compile the fully pipelined radix-2^51 field multiplier.

mul51_cell_hdl

Compile one six-stage 51-bit multiplier for inexpensive technology-mapping experiments.

scalar_reduce_hdl

Compile the initiation-interval-one scalar reducer.

sha512_compress_hdl

Compile one iterative SHA-512 compression lane.