Module planner 

The shared SHA-512 line as a component of the chip planner/TUI.

The line supplies "sha512 blocks" to every client on it (Ed25519 sign and verify). DSig’s chain lanes do not use it; they carry their own hashers. Its allowance comes out of the chip budget before the signature engines share the rest (the SHA part of the LUT split).

What a line is made of

One core. The clients’ arbiter (rhdl_ed25519_scalable_core:: sha_client) feeds a single in-order core, so a line is one of:

Core	Blocks/clock	LUT (routed)
Sha512Pipeline, 80 stages	1	FULL_LUT = 62,252
Sha512Folded40	½	40,047
Sha512Folded20, 16, 10, 8, 5, 4	S / 80	20,880, 16,887, 11,295, 9,431, 6,778, 5,851
Sha512Folded2	1/40	3,509

(ROUTED_LUT.) The smallest line hashes 5.1M blocks per second, enough for about 1.7M Ed25519 signatures. fastest picks the core that hashes the most in a LUT budget; smallest the cheapest core that hashes a given rate (a full pipeline when nothing is enough).

How big: auto or by hand

Knob	Range	Default
LUT cap	0 – 432,000 (SHA_LINE_MAX_LUT)	65,000 (manual: a full pipeline, 1 block/clock)
DSP cap	0 – 20	20
size	auto / manual	auto

• Auto (the default): the line never limits the chip. The planner asks the line for the smallest build that hashes what the engines want ([Component::size_for]), gives the engines what that leaves, and repeats until the size settles (rhdl_fpga_planner::plan_chip). The LUT cap then shows the size it settled on.
• Manual: the LUT cap is the line’s guaranteed allowance (moving it, or the TUI’s LUT split row, switches to manual). The planner can still lend the line LUTs nobody else uses, and it grows past the cap up to LARGEST_LINE_LUT (one full pipeline). A cap of 0 means no line.

The LUT costs are routed out of context (Vivado 2023.2, 4.878 ns = 205 MHz, every core with positive slack, +0.59 to +1.17 ns; 2026-10-16/17), not in-chip: a placed chip can differ. The rates are the cores’ design rates (S / 80, one block per clock for the pipeline), checked in native simulation. The earlier Yosys estimates (87,178 for the pipeline, folded::folded_lut) were 20-40 % high.

Re-exports

pub use crate::folded::folded_lut;

Structs

Line

A line: how many cores of each kind (cores order).

Sha512

The shared SHA-512 line.

Constants

FULL_LUT

LUTs of one full pipeline, routed out of context at 4.878 ns (WNS +0.638 ns). Yosys estimated 87,178.

LARGEST_LINE_LUT

The largest line: one full pipeline, 1 block per clock (the arbiter drives one core).

LINE_LATENCY

Latency of every core in cycles (the folded cores match the pipeline’s).

ROUTED_LUT

Routed out-of-context LUTs of each folded core, (stages, LUT), at 4.878 ns (Vivado 2023.2, 2026-10-16/17; WNS +0.59 to +1.17 ns).

SHA_LINE_DSP

Default and largest DSP allowance of the line.

SHA_LINE_LUT

The default LUT allowance of a manual line.

SHA_LINE_MAX_LUT

Largest LUT allowance the knob takes (about five full pipelines). A bigger allowance takes LUTs from the engines (the LUT split).

Functions

cores

The kinds of core a line can hold: (ring stages, LUTs). Stages are also the rate in 1/80 blocks per clock; 80 is the full pipeline.

fastest

The one-core line that hashes the most within luts (ties: fewer LUTs); no line when not even the smallest core fits.

smallest

The cheapest one-core line that hashes at least units / 80 blocks per clock; above one block per clock, a full pipeline (the line then limits the chip).