Struct DsigVerify 

pub struct DsigVerify {
    pub chain_hash: usize,
    pub sha_shared: bool,
    pub hbss: Hbss,
    pub message64: bool,
    pub table_rounds: u32,
    pub table_uram: bool,
    pub own_ed25519: bool,
}

DSig verification (built: crate::verify).

A verify unit has three chain lanes and one BLAKE3 lane, like a slice. Its rate is set by its busier side: chain steps over three lanes, or BLAKE3 compressions on one lane. The Ed25519 certificate check (1 − h of verifications) is done by the Ed25519 verify component, not here. Its knobs must match the signer’s for the two to verify each other.

Fields

chain_hash: usize

0 Haraka-512, 1 BLAKE3, 2 SHA-512 (must match the signer).

sha_shared: bool

SHA-512 chains on the shared line instead of own pipelines.

hbss: Hbss

The hash-based scheme (must match the signer).

message64: bool

Profile 2: 64-byte messages (must match the signer).

table_rounds: u32

Table rounds of the unit’s three Haraka lanes (0..=6, see table_lane, or AUTO_TABLE_ROUNDS, the default). Independent of the signer’s: the verify unit is separate hardware, so a BRAM-bound chip can give tables to one and LUT S-boxes to the other.

table_uram: bool

Table lookups beyond the share’s block RAM go to its UltraRAM, as Dsig::table_uram. Model. On by default, like the signer’s.

own_ed25519: bool

Certificates are checked by the verifier’s own Ed25519 verify core (as built) instead of the chip’s Ed25519 verify module.

Implementations

impl DsigVerify

pub fn uses_shared_line(&self) -> bool

Whether the chain lanes hash on the shared SHA-512 line.

pub fn core_rest() -> (f64, f64)

LUTs and block RAM of a verify core beyond its three chain lanes: the measured core minus its three lanes (as the lane model prices them). The BLAKE3 lane, scheduler, banks and cache are all in here.

pub fn unit_cost(&self) -> Cost

Cost of one verify unit: three chain lanes of the chosen hash, the measured rest of the core, and the unit’s HBM I/O.

pub fn ed25519_cost(&self) -> Cost

The embedded Ed25519 verify core, when certificates are checked inside.

pub fn is_measured(&self) -> bool

Whether this configuration is the one measured (costs from Vivado, period from simulation).

pub fn units_cost(&self, units: u32, share: &Share) -> (Cost, f64)

Cost of units units inside share, and the URAM their tables took.

Without “table RAM” on URAM this is units × unit_cost. With it, the table block RAM that the share cannot hold moves to UltraRAM, and every lane gets a TABLE_LOADER_LUT loader.

pub fn cycles_per_verify(&self) -> f64

Cycles per verification of one unit: the busier of chain steps over three lanes and BLAKE3 compressions on one lane (35 for the built scheme: 105 / 3 versus 29). The built scheme uses the measured period.

pub fn latency_cycles(&self) -> f64

Idle latency of the hash path. The built scheme uses the measured figure; others scale it by their chain and commitment depth.

Trait Implementations

impl Clone for DsigVerify

fn clone(&self) -> DsigVerify

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Component for DsigVerify

How the chip planner talks to the verifier model.

fn name(&self) -> String

The row label.

fn role(&self) -> Role

Tells the planner this component supplies DSig verifications.

fn knobs(&self) -> Vec<Knob>

Knobs: 0 HBSS, 1 chain hash, 2 SHA lanes, 3 Winternitz w, 4 batch K, 5 table rounds, 6 table RAM. The first five are shared with the signer (the TUI shows them under DSig sign); the last two are the unit’s own.

fn set_knob(&mut self, index: usize, value: f64)

Applies a knob change, clamping out-of-range indices.

fn unavailable(&self) -> Option<String>

HORS has no plan yet.

fn build_flags(&self, plan: &Plan) -> BuildFlags

DSIG_VERIFY_UNITS and the lanes’ table mask; what is not built yet is named.

fn plan(&self, share: &Share, cx: &Context) -> Option<Plan>

As many identical verify units as the share’s LUTs and BRAM allow.

Unlike the signer, units scale one by one, so the plan is a simple division. The Ed25519 check on cache misses is planned separately.

fn fixed(&self) -> Option<Cost>

An allowance taken off the top of the budget before the powers divide the rest (the SHA line’s part of the LUT split), or None to take a share of its side.

fn size_for(&self, _per_second: f64, _cx: &Context) -> Option<Cost>

A line that sizes itself to demand (“auto”): the allowance of its smallest build that supplies per_second units of what it supplies (SHA-512 blocks) at cx’s clock, or None when its size is set by hand (the default). The planner ([plan_chip]) calls it with the demand of the chip it plans, so the line never limits the chip.

fn resize(&mut self, _allowance: Cost)

Remember the allowance the planner settled on for an auto-sized line ([apply_layout] calls it), so fixed and the next plan start from it.

fn ubft(&self) -> bool

A uBFT module: a service built to sit beside a uBFT replica (its streams and key slots), or the replica’s own footprint. Only the uBFT modes plan it, and they plan nothing else ([Mode::admits]).

impl Debug for DsigVerify

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for DsigVerify

Haraka-512 chains, the built HBSS and auto table rounds, matching the default signer; certificates on the chip’s Ed25519 verify module.

fn default() -> Self

Returns the “default value” for a type.