Struct Dsig 

pub struct Dsig {
    pub chain_hash: usize,
    pub sha_shared: bool,
    pub hbss: Hbss,
    pub message64: bool,
    pub sbox_ram: bool,
    pub blake3_dsp: bool,
    pub own_ed25519: bool,
    pub table_rounds: u32,
    pub table_uram: bool,
}

The DSig component.

The signer as the chip planner sees it. Its fields are the planner knobs; [Component::knobs] shows them and [Component::set_knob] changes them. Only the default chain hash (Haraka-512) with the default HBSS matches the preserved DSIG_FPGA_W4_HARAKA_BLAKE3_V1 profile.

Fields

chain_hash: usize

0 Haraka-512, 1 BLAKE3, 2 SHA-512.

Index into the hash name list; picks the lane type of every slice (the DSIG_CHAIN build variable).

sha_shared: bool

SHA-512 chains only: hash on the shared SHA-512 line instead of DSig’s own pipelines (model). The line’s blocks then go to DSig as well as Ed25519, so the planner balances them.

hbss: Hbss

The hash-based scheme and its batch size.

message64: bool

Profile 2: sign 64-byte messages (DSIG_MESSAGE_BYTES=64).

sbox_ram: bool

Fill the share’s spare RAM with Haraka S-boxes.

true uses config::Build::fill_within; false keeps every S-box in LUTs. Only matters for Haraka-512.

blake3_dsp: bool

BLAKE3 adders in DSPs.

Planned and estimated only: trades LUTs for DSPs in every BLAKE3 lane.

own_ed25519: bool

Certify batches with DSig’s own Ed25519 core (as built) instead of the chip’s Ed25519 sign module.

table_rounds: u32

AES rounds of every Haraka lane, from round 3 up, computed with block-RAM T-tables (0..=6; see table_lane), or AUTO_TABLE_ROUNDS (the default) to pick the fastest inside the share, so block RAM the share leaves over becomes signing speed. 0 is build v3 (LUT S-boxes, routed), 6 is build v5 (rounds 3–8, synthesis). Any value above 0 overrides “S-box RAM”: the remaining S-boxes stay in LUTs.

table_uram: bool

T-table lookups that do not fit the share’s block RAM move to its spare UltraRAM (LOOKUPS_PER_URAM, plus a TABLE_LOADER_LUT loader per lane). Model: the URAM T-table and its loader are not built. On by default (the user’s choice: spare URAM should speed DSig up); the detail line and not_buildable mark a plan that uses it.

Implementations

impl Dsig

pub const MAX_SLICES: u32 = 16

Largest slice count the planner may choose. Every count from 1 is tried; 2, 4 and 8 are built (DSIG_SLICES=N, see Dsig::BUILT_SLICES); the rest are a model with the same per-slice cost (1 needs 7-bit key numbers in a slice, today 6).

pub const BUILT_SLICES: [u32; 3]

Slice counts DSIG_SLICES accepts.

pub fn uses_shared_line(&self) -> bool

Whether the chain lanes hash on the shared SHA-512 line.

pub fn placement(&self, slices: u32, share: &Share) -> Build

The S-box placement for slices slices inside share.

Only Haraka lanes with “S-box RAM” on place S-boxes. The T-tables (and their URAM spill) take RAM first; the S-boxes of the remaining rounds then fill what is left, block RAM first (no loader), then UltraRAM, in dual-port pairs: four per BRAM36, two per URAM.

pub fn cost(&self, slices: u32, share: &Share) -> (Cost, String)

Cost of slices slices inside share with the current knobs, plus a description.

The whole kernel: slices slices, the Ed25519 core and the glue. The returned string is the one-line description shown in the planner.

pub fn rate(&self, slices: u32, mhz: f64) -> f64

Signatures per second of slices slices at mhz.

The slice ceiling slices × f / key period; with DSig’s own Ed25519 core also capped by the certificate ceiling K × f / 895 (otherwise the planner sizes the chip’s Ed25519 signer for 1/K of this rate). Unlike config::Build::signatures_per_second it leaves out the frame-write stage, which is never the limit at these slice counts in that model. With the shared SHA-512 line, the line’s supply is checked by the planner through this plan’s demand, not here.

Trait Implementations

impl Clone for Dsig

fn clone(&self) -> Dsig

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Component for Dsig

How the chip planner talks to the DSig signer.

fn name(&self) -> String

The row label in the planner.

fn role(&self) -> Role

Tells the planner this component supplies DSig signatures.

fn knobs(&self) -> Vec<Knob>

The knobs, in the order [Component::set_knob] indexes them: 0 HBSS, 1 chain hash, 2 SHA lanes, 3 Winternitz w, 4 batch K (these five shared with DsigVerify), 5 S-box RAM, 6 BLAKE3 adders, 7 Ed25519 certificates, 8 table rounds, 9 table RAM (the last two the signer’s own; the verify unit has separate ones).

fn set_knob(&mut self, index: usize, value: f64)

Applies a knob change from the planner. value is the chosen index as a float; out-of-range indices are clamped to the last choice.

fn unavailable(&self) -> Option<String>

HORS has no plan yet.

fn plan(&self, share: &Share, cx: &Context) -> Option<Plan>

The largest slice count whose cost fits share, or None if even one slice does not fit (or the HBSS is HORS, which has no model).

Sizes are tried smallest first. The first size that does not fit stops the search, and the resource it ran out of becomes the plan’s limit, so the planner can tell the user what to add.

fn build_flags(&self, plan: &Plan) -> BuildFlags

The build variables that build plan (DSIG_SLICES, DSIG_CHAIN and, for Haraka, DSIG_TABLE_MASK and DSIG_SBOX_PLACEMENT; see build.rs).

The slice count is recovered from the plan’s detail line (it starts with the count). Haraka builds also get the matching DSIG_SBOX_PLACEMENT, which needs the share; the TUI writes these for the plan it shows, so the placement is recomputed from the plan’s own RAM cost.

fn fixed(&self) -> Option<Cost>

An allowance taken off the top of the budget before the powers divide the rest (the SHA line’s part of the LUT split), or None to take a share of its side.

fn size_for(&self, _per_second: f64, _cx: &Context) -> Option<Cost>

A line that sizes itself to demand (“auto”): the allowance of its smallest build that supplies per_second units of what it supplies (SHA-512 blocks) at cx’s clock, or None when its size is set by hand (the default). The planner ([plan_chip]) calls it with the demand of the chip it plans, so the line never limits the chip.

fn resize(&mut self, _allowance: Cost)

Remember the allowance the planner settled on for an auto-sized line ([apply_layout] calls it), so fixed and the next plan start from it.

fn ubft(&self) -> bool

A uBFT module: a service built to sit beside a uBFT replica (its streams and key slots), or the replica’s own footprint. Only the uBFT modes plan it, and they plan nothing else ([Mode::admits]).

impl Debug for Dsig

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Dsig

Haraka-512 chains, the built HBSS, auto table rounds (as many T-table rounds as the share’s block RAM makes fastest), BLAKE3 adders in LUTs, certificates from the chip’s Ed25519 sign module (the modular chip of the paper). Set “Ed25519 certificates” to “inside DSig” for the routed, measured kernel; turn “S-box RAM” to “fill” to explore the (estimated) RAM placement.

fn default() -> Self

Returns the “default value” for a type.